Silicon Design Verification Lead, TPU, Google Cloud

Silicon Design Verification Lead, TPU, Google Cloud
Minimum qualifications
Bachelor's degree in Electrical Engineering or equivalent practical experience.
10 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
8 years of experience with verification methodology such as Universal Verification Methodology (UVM).
4 years of experience in people management, developing employees.
Experience with SystemVerilog, SystemVerilog Assertions (SVA) and functional coverage.