Senior Digital ASIC Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Ciena’s WaveLogic products are central to advancing high-performance optical networking solutions. This role contributes to the design and integration of next-generation ASIC technologies that power critical telecommunications infrastructure. The position enables delivery of scalable and high-quality silicon solutions through cross-functional collaboration.
How you will make an impact:
Contribute to top-level ASIC design and integration for WaveLogic products
Interpret architecture and functional specifications and collaborate with systems engineers and architects
Develop and assemble top-level RTL designs integrating multiple IP blocks
Maintain and enhance technology-specific libraries for advanced semiconductor nodes
Own and manage tool flows supporting ASIC top-level integration
Create timing constraints and analyze synthesis, timing, layout, and backend reports
Perform lab validation of ASIC prototypes and production silicon
The must haves:
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science
Experience: 5+ years of experience in ASIC design.
Ability to work independently while contributing within a team environment
Application of structured approaches to solving complex technical problems
Written and verbal communication in English within technical environments
Utilization of Verilog, SystemVerilog, and Python in digital design workflows
Application of digital design concepts including synthesis, static timing analysis (STA), timing closure, and asynchronous clock domain crossing
Nice to haves:
Exposure to programming languages including C, C++, and SystemC
Use of scripting or object-oriented programming approaches in engineering workflows
Experience with ASIC verification.
Pay Range:
The annual pay range for this position is C$109,000 - C$174,000.
#LI-BS1
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.