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Analog RF & Mixed-Signal Verification Engineer / Architect

nxp semiconductors · зарплата не указана · Bangalore · сайт компании · опубликовано 5 июня 2026 г.

Компания nxp semiconductors
Источник сайт компании
Опубликовано 5 июня 2026 г.
Зарплата зарплата не указана

Описание вакансии

The Analog RF & Mixed-Signal Verification Engineer / Architect is responsible for defining and executing comprehensive design verification strategies to enable robust Design Enablement solutions for SoC development. The role focuses on ensuring that foundry processes, PDKs, tools, and methodologies work seamlessly together by using Analog, RF, and Mixed-Signal IPs as validation vehicles. The individual will plan, architect, and develop integration test frameworks to evaluate compatibility, stability, and scalability across platforms. This includes qualitative and quantitative analysis, as well as impact assessment of different IP, tool, and methodology versions. The role collaborates closely with AMS flow teams, PDK, IP teams and EDA vendors to enable new features and supports deployment across advanced technology nodes from 28nm to 5nm, while leveraging AI-driven approaches to drive innovation, automation, and improvements in quality and productivity.
Required skillset:
Strong expertise in Analog, RF, and Mixed-Signal verification methodologies and EDA tools
Familiarity with foundry PDKs, process components, and their configuration, including technology files
Experience with Spectre, HSPICE, Cadence AMS Designer
Proficiency in RF and EM tools such as Keysight ADS, HFSS, EMX, Clarity
Strong understanding of co-simulation (Analog + Digital + RF domains)
Experience in functional, structural, and integration-level verification
Scripting skills in SKILL, TCL, Python, or similar
Desired skillset:
Strong fundamentals in Analog and RF circuit blocks, such as amplifiers, PLLs, ADC/DACs, mixers, oscillators, filters, and RF front-end components
Knowledge of reliability and aging analysis (BTI, HCI, EM effects)
Expertise in building top-level verification environments for IP/subsystems
Understanding of parasitic effects, PVT variations, and post-layout verification
Soft Skills
Strong technical leadership and mentoring capabilities
Good problem-solving and analytical thinking
Clear communication and documentation skills
Ability to drive initiatives and influence technical decisions
Strong ownership and accountability for deliverables
Academics & Experience Level
Education: B.Tech/M.Tech in Electronics and Communication / Electrical and Electronics or related fields of engineering
Experience: 8+ years of experience in Semiconductor / EDA domain
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